Nortel Networks NN43001-301 Manuel d'utilisateur Page 159
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Description 159
In an isolated private network, the clock controller can operate in free run
mode and act as a master clock to be tracked by other PBX systems in
the private network.
Hierarchical synchronization
Figure 59 "Hierarchical Synchronization" (page 159) provides a general
view of the Digital Network Clock Synchronization including the four stratum
level Node Categories. Stratum 1 being the most accurate and Stratum 4
being the least accurate. System clocking meets Node Category E Stratum
4 requirements. Also shown are ways of providing a Secondary Clock
Source while preventing timing loops.
Figure 59
Hierarchical Synchronization
Nortel Communication Server 1000
ISDN Primary Rate Interface Installation and Commissioning
NN43001-301 02.03 Standard
Release 5.5 7 December 2007
Copyright © 2003-2007, Nortel Networks
.
- ISDN Primary Rate Interface 1
- 2.0 Mb DTI implementation 237 6
- 2.0 Mb PRI implementation 257 6
- 2.0 Mb ISL implementation 283 6
- Nonstandard cables 295 6
- Procedures 7
- New in this release 9
- NN43001-301 02.03 Standard 10
- Release 5.5 7 December 2007 10
- How to get help 11
- 12 How to get help 12
- Intended audience 14
- Related information 14
- Figure 1 18
- D-Channel Handler description 20
- NT6D11 DCH 20
- QPC757 DCH 21
- QPC757 faceplate 22
- NT6D80 MSDL 23
- MSDL/PRI interface 24
- MSDL faceplate 24
- Standard PRI cards 25
- NT8D72 PRI2 25
- Carrier interface 27
- Echo canceller interface 28
- QMT21 High Speed Data Module 28
- Free run (non-tracking) mode 29
- Reference clock errors 29
- QPC720 PRI 30
- QPC720 faceplate 31
- QPC720 Cable requirements 32
- Echo Canceller interface 32
- 64 T-link version 2 protocol 33
- Disk drive hardware 34
- NT5D97 faceplate 35
- Enable/Disable Switch 37
- ENET LEDs 37
- CPU capacity 40
- Power requirements 40
- Testability and diagnostics 40
- E1 carrier cables 41
- NTCK45AA cable 42
- NTCK78AA cable 44
- Reference clock cables 45
- MSDL/DCH cables 46
- Cable diagrams 47
- Figure 16 48
- Clock for the NT5D97 49
- Clock operation 49
- Figure 18 50
- Automatic clock recovery 51
- Automatic clock switching 51
- Clock configurations 52
- Figure 20 55
- Clock Controller - Option 2 55
- Figure 21 56
- Clock Controller - Option 3 56
- NT5D12 Dual-port DTI/PRI 57
- D-Channel and MSDL interface 58
- NT5D12 faceplate 59
- Figure 23 60
- Port Out of Service LEDs 62
- NT5D12 Dual-port DTI/PRI 63 63
- NT5D12 Cable requirements 65
- Trunk Tip/Ring cables 66
- NT5D16AA 66
- NT5D16AA cable 67
- MSDL/DCHI cables 68
- External DCHI cable 68
- External MSDL cable 69
- NT5D12 Dual-port DTI/PRI 75 75
- Figure 31 75
- Clock Controller - Option 1 75
- Figure 32 76
- NT5D12 Dual-port DTI/PRI 77 77
- Figure 33 77
- Figure 34 78
- Clock Controller - Option 4 78
- DCH installation 79
- DIP switch settings 80
- Protocol selection 80
- Valid switch combinations 81
- Jumper settings 82
- Port addressing modes 83
- Port 0 Mode selection 83
- Port 1 mode selection 83
- Port address switch settings 84
- 86 DCH installation 86
- Procedure 2 86
- Install the QPC757 DCH 87
- 88 DCH installation 88
- Figure 38 88
- Remove the QPC757 DCHI 90
- Install the MSDL 95
- Replace the MSDL 98
- Replace the MSDL 99 99
- NT8D72 and QPC720 PRI card 101
- Cable requirements 102
- Cable requirements 103 103
- Figure 41 103
- Figure 42 104
- Figure 43 105
- Cable requirements 105 105
- Figure 44 106
- Cable requirements 107 107
- Figure 45 107
- Figure 46 108
- Cable requirements 109 109
- Figure 47 109
- Figure 48 110
- Cable requirements 111 111
- Figure 49 111
- Figure 50 112
- Cable requirements 113 113
- Figure 51 113
- Switch settings 120
- Switch settings 121 121
- Figure 53 121
- Procedure 12 124
- Procedure 13 125
- Contents 127
- Introduction 127
- NT5D97 circuit card locations 127
- Port definitions 128
- Figure 55 130
- DIP switches for NT5D97AA/AB 130
- Impedance level and unit mode 131
- Transmission mode 131
- Line build out 131
- Receiver impedance 132
- NT5D97AA/AB 132
- NT5D97AD DIP switch settings 134
- Figure 56 135
- Trunk 0 switches 136
- Trunk 1 switches for NT5D97AD 137
- NT5D97AD 137
- MSDL external card 138
- Install the NT5D97 DDP2 139
- Remove the NT5D97 DDP2 140
- Configure the NT5D97 DDP2 141
- NT5D12 Dual-port DTI/PRI card 143
- NT5D12 switch settings 145
- Line Build Out 146
- Receiver Impedance 146
- Ring ground switches 146
- NT5D12 switch settings 149 149
- Figure 57 149
- Install the NT5D12 DDP 150
- Remove the NT5D12 DDP 152
- Configure the NT5D12 DDP 153
- Description 156
- Supported Clock Controllers 157
- NTRB53 Clock Controller 157
- Synchronization methods 158
- Plesiosynchronous operation 158
- Mesosynchronous operation 158
- Hierarchical synchronization 159
- Stratum levels 160
- Frame slip 160
- Guidelines 161
- Figure 60 162
- Figure 61 162
- Primary Source fails 163
- Figure 63 164
- Description 165 165
- Figure 64 165
- Figure 65 166
- Modes of operation 167
- Tracking mode 167
- Installation procedures 168
- Set switches 169
- Start the Clock Controller 171
- Clock Controller commands 171
- TRCK PCK (for primary) 174
- SCLK (for secondary) 174
- FRUN (for free-run) 174
- Group System 175
- ISL installation 179
- DCHI switch settings 180
- MSDL switch settings 181
- Shared mode 182
- Figure 70 183
- ISL in shared mode 183
- Figure 71 183
- 184 ISL installation 184
- Figure 72 184
- QMT11 switch settings 187
- QMT8 switch settings 188
- QMT21C switch settings 188
- 190 ISL installation 190
- Echo canceller installation 191
- Electromagnetic Interference 192
- Figure 75 193
- PRI to echo canceller cabling 193
- 1.5 Mb PRI implementation 195
- Hardware description 196
- NTRB21 TMDI card 197
- Shelf slot assignments 197
- NTAK09 DTI/PRI circuit card 198
- ATTENTION 199
- Clocking modes 200
- Shelf slot assignment 201
- Clock controller LED states 201
- Install PRI hardware 203
- 204 1.5 Mb PRI implementation 204
- Figure 78 204
- Install PRI hardware 207 207
- Procedure 28 207
- Installing the NTAK09 209
- 218 1.5 Mb PRI implementation 218
- 1.5 Mb DTI implementation 219
- Install DTI hardware 220
- Connect the cables 221
- 1.5 Mb ISL implementation 227
- Dedicated mode 228
- Using dialup modems 228
- Basic ISL implementation 232
- Implement shared mode 236
- 2.0 Mb DTI implementation 237
- NTAK10 2.0 Mb DTI card 238
- Set the switches 239
- Switch S3 - Mode of operation 240
- Insert the NTAK10 240
- DTI software implementation 241
- Task summary list 242
- 2.0 Mb PRI implementation 257
- Install the NTAK79 PRI card 261
- 262 2.0 Mb PRI implementation 262
- Figure 83 262
- NTAK79 with switch locations 262
- Insert the NTAK79 264
- NTBK05DA pinouts 265
- NTBK05CA pinouts 265
- Install the NTBK50 PRI card 266
- Figure 85 267
- NTBK50 with switch locations 267
- 270 2.0 Mb PRI implementation 270
- Figure 86 270
- Daughterboard installation 270
- Insert the NTBK50 271
- PRI software implementation 272
- 282 2.0 Mb PRI implementation 282
- 2.0 Mb ISL implementation 283
- ISL hardware requirements 285 285
- Figure 89 285
- ISL hardware installation 286
- ISL software implementation 288
- 294 2.0 Mb ISL implementation 294
- Nonstandard cables 295
- NT5K40AA, NT5K41AA, NT5K86AA 296
- NT8D7206, NT8D7207 296
- NT8D7205 299
- NT8D83 PRI/DTI to I/O cable 301
- NT8D85 Network to IPE cable 302
- NT8D86 Network to I/O cable 302
- NTND26 PRI to MSDL cables 303
- 304 Nonstandard cables 304
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